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| DATASHEET QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE Description The ICS557-05A is a spread-spectrum clock generator that supports PCI-Express requirements. It is used in PC or embedded systems to substantially reduce electro-magnetic interference (EMI). The device provides four differential HCSL or LVDS high-frequency outputs with spread spectrum capability. The output frequency and spread type are selectable using external pins. ICS557-05A Features * Packaged in 20-pin TSSOP * Available in RoHS 5 (green) or RoHS 6 (green and lead free) complaint package * * * * * * * * * Supports PCI-Express applications Four differential spread spectrum clock outputs Spread spectrum for EMI reduction Uses external 25 MHz clock or crystal input Power down pin turns off chip OE control tri-states outputs Spread and frequency selection via external pins Spread Bypass option available Industrial temperature range available Block Diagram VDD 2 PD OE SEL[2:0] 3 Spread Spectrum/ Output clock selection Spread Spectrum Circuitry CLKOUTA 25 MHz crystal or clock X1 Clock Oscillator X2 CLKOUTA CLKOUTB PLL Clock Synthesis CLKOUTB CLKOUTC CLKOUTC CLKOUTD CLKOUTD 2 GND Rr(IREF) Optional tuning crystal capacitors IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 1 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG Pin Assignment VDDXD S0 S1 S2 X1 X2 PD OE GNDXD IREF 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CLKA CLKA CLKB CLKB GNDODA VDDODA CLKC CLKC CLKD CLKD 20-pin (173 mil) TSSOP Spread Spectrum Selection Table S2 S1 S0 Spread% Spread Type 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 -0.5 Down -1.0 Down -1.5 Down No Spread Not Applicable -0.5 Down -1.0 Down -1.5 Down No Spread Not Applicable Output Frequency 100 100 100 100 200 200 200 200 IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 2 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name VDDXD S0 S1 S2 X1 X2 PD OE GND IREF CLKD CLKD CLKC CLKC VDDODA GND CLKB CLKB CLKA CLKA Pin Type Power Input Input Input Input Output Input Input Power Output Output Output Output Output Power Power Pin Description Connect to +3.3 V digital supply. Spread spectrum select pin #0. See table above. Internal pull-up resistor. Spread spectrum select pin #1. See table above Internal pull-up resistor. Spread spectrum select pin #2. See table above. Internal pull-up resistor. Crystal connection. Connect to a fundamental mode crystal or clock input. Crystal connection. Connect to a fundamental mode crystal or leave open. Powers down all PLL's and tri-states outputs when low. Internal pull-up resistor. Provides output on, tri-states output (High = enable outputs; Low = disable outputs). Internal pull-up resistor. Connect to digital ground. Precision resistor attached to this pin is connected to the internal current reference. Selectable 100/200 MHz spread spectrum differential Compliment output clock D. Selectable 100/200 MHz spread spectrum differential True output clock D. Selectable 100/200 MHz spread spectrum differential Compliment output clock C. Selectable 100/200 MHz spread spectrum differential True output clock C. Connect to +3.3 V analog supply. Connect to analog ground. Output Selectable 100/200 MHz spread spectrum differential Compliment output clock B. Output Selectable 100/200 MHz spread spectrum differential True output clock B. Output Selectable 100/200 MHz spread spectrum differential Compliment output clock A. Output Selectable 100/200 MHz spread spectrum differential True output clock A. IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 3 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG Application Information Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS557-05A must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. Load Resistors RL Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. Output Termination The PCI-Express differential clock outputs of the ICS557-05A are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-05A can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS557-05A. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 F should be connected between VDD and GND pairs (1,9 and 15,16) as close to the device as possible. On chip capacitors- Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (CL-12)*2 in this equation, CL=crystal load capacitance in pf. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 8 pF. [(16-12)x2]=8. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50 then Rr = 475 , (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF. IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 4 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG Output Structures IREF =2.3 mA 6*IREF R R 475W See Output Termination Sections - Pages 3 ~ 5 General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-05A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 5 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch inch ohm ohm Unit inch inch Unit inch inch PCI-Express Device Routing L1 RS L1' RS L2 L2' RT L3' RT L3 L4 L4' ICS557-05A Output Clock PCI-Express Load or Connector Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 0.52 V 0.175 V 500 ps 500 ps tOF 0.52 V 0.175 V IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 6 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG LVDS Compatible Layout Guidelines LVDS Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. RP RQ RT L3 length, Route as coupled 50 ohm differential trace. L3 length, Route as coupled 50 ohm differential trace. Dimension or Value 0.5 max 0.2 max 100 100 150 Unit inch inch ohm ohm ohm LVDS Device Routing L1 RQ L1' L3 L3' RP RT ICS557-05A Clock Output L2' L2 RT LVDS Device Load Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 500 ps tOF 1250 mV 1150 mV 1250 mV 1150 mV IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 7 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-05A. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD, VDDA All Inputs and Outputs Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Storage Temperature Junction Temperature Soldering Temperature ESD Protection (Input) 5.5 V Rating -0.5 V to VDD+0.5 V 0 to +70 C -40 to +85 C -65 to +150 C 125 C 260 C 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C Parameter Supply Voltage Input High Voltage1 Input Low Voltage 1 2 Symbo l V VIH VIL IIL IDD IDDOE IDDPD Conditions Min. 3.135 2.0 VSS-0.3 Typ. Max. 3.465 VDD +0.3 0.8 5 Units V V A mA mA A Input Leakage Current 0 < Vin < VDD 50, 2 pF load @100 MHz OE =Low No load, PD =Low Input pin capacitance Output pin capacitance CLK outputs OE, SEL, PD pins -5 105 40 500 Operating Supply Current Input Capacitance Output Capacitance Pin Inductance Output Resistance Pull-up Resistance CIN COUT LPIN Rout RPUP 7 6 5 3.0 110 pF pF nH k k 1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included. IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 8 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG AC Electrical Characteristics - CLKOUTA/CLKOUTB Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85 C Parameter Input Frequency Output Frequency Output High Voltage1,2 Output Low Voltage Crossing Point Voltage1,2 Crossing Point Voltage1,2,4 Jitter, Cycle-to-Cycle1,3 Modulation Frequency Rise Time Fall Time 1,2 1,2 Symbo l Conditions Min. Typ. 25 Max. Units MHz HCSL termination LVDS termination VOH VOL Absolute Variation over all edges 660 -150 250 700 0 350 200 100 850 27 550 140 80 MHz MHz mV mV mV mV ps kHz ps ps ps % us us ms ms Spread spectrum tOR tOF From 0.175 V to 0.525 V From 0.525 V to 0.175 V At crossing point Voltage 30 175 175 45 31.5 332 344 33 700 700 50 55 10 10 1,2 Skew between outputs Duty Cycle 1,3 5 5 Output Enable Time Power-up Time All outputs All outputs tSTABLE From power-up VDD=3.3 V 3.0 3.0 tSPREAD Settling period after spread change Output Disable Time Spread Change Time 1 2 3 Test setup is RL=50 ohms with 2 pF, Rr = 475 (1%). Measurement taken from a single-ended waveform. Measurement taken from a differential waveform. at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its 4 Measured 5 CLKOUT PD= low. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 93 78 65 20 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 9 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch inch ohm ohm Unit inch inch Unit inch inch PCI-Express Device Routing L1 RS L1' RS L2 L2' RT L3' RT L3 L4 L4' ICS557-03 Output Clock PCI-Express Load or Connector Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 0.52 V 0.175 V 500 ps 500 ps tOF 0.52 V 0.175 V IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 10 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters 20 Inches* Min Max Symbol A A1 A2 b c D E E1 e L a aaa Min Max E1 INDEX AREA E 12 D 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A2 A1 A c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number ICS557G-05A ICS557G-05AT ICS557G-05ALF ICS557G-05ALFT ICS557GI-05A ICS557GI-05AT ICS557GI-05ALF ICS557GI-05ALFT Marking ICS557G-05A ICS557G-05A 557G-05ALF 557G-05ALF 557GI-05A 557GI-05A 557GI-05AL 557GI-05AL Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP Temperature 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE 11 ICS557-05A REV H 092407 ICS557-05A QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE PCIE SSCG Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-4522 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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